1. Field of the Invention
This disclosure relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same.
2. Description of the Related Art
In general, in order to improve a design performance goals such as high integration and high speeds, a semiconductor device is fabricated such that an arrangement of a semiconductor circuit formed on a semiconductor substrate is changed or a certain circuit is added to an existing semiconductor circuit.
High integration is obtained by reducing a design rule, and through this reduction a high speed can be implemented. Reduction of a design rule involves decreasing the size of a pitch between components of a semiconductor device. However, due to the reduction of the design rule, a photolithography process may not be stably performed on a semiconductor substrate. This is because light passing through a photo mask during a photolithography process causes more severe dispersion and interference on a semiconductor substrate having a photo resist film than before the reduction of a design rule.
Changing the arrangement of the semiconductor circuit to improve a design performance adds an extra burden to a fabricating process because the photolithography process condition should be set again before and after a circuit arrangement changes in consideration of a process margin between a cell array region and a peripheral circuit region. Adding the certain circuit to the existing semiconductor circuit requires a previous work that makes out a design rule of a desired semiconductor device and then trains again an engineer portions to be monitored a semiconductor substrate. Therefore, methods of changing the arrangement of the semiconductor circuit and adding the certain circuit to the existing semiconductor circuit need much efforts and time of engineers related to fabrication of a semiconductor device.
Recently, many resolutions to increase a design performance by using a semiconductor fabrication process have been suggested. Such resolutions relate to introducing a new material or changing a shape of components of a semiconductor device. Introducing new material decreases a resistance of the circuit wire, thereby improving a wiring capability of a semiconductor device. Changing a shape of components of a semiconductor device maximizes an electrical capability of components, thereby doubling the driving ability of a semiconductor device.
On the other hand, U.S. Pat. Publication No. 2002-79536 to Takashi Terauchi et al. disclosed a semiconductor device that improves design performance by changing the shape of components of a semiconductor device.
According to the U.S. Pat. Publication No. 2002-79536, the semiconductor device comprises lower and upper interlayer insulating layers sequentially placed on a semiconductor substrate, and two adjacent wires are placed between the lower and upper interlayer insulating layers. The lower and upper interlayer insulating layers are oxide films, and each of the wires has a silicon nitride layer pattern, a conductive layer pattern, and a capping layer pattern that are stacked in sequence. The wires can be used as bit line wires in a DRAM cell array region. Spacers are placed on side walls of the wires, and the spacers and the capping layer pattern are silicon nitride layers.
Next, a first contact hole is placed to be self-aligned between the wires by penetrating a predetermined region of the lower and upper interlayer insulating layers, exposing a portion of the semiconductor substrate. By using the first contact hole, the lower and upper interlayer insulating layers are wet-etched to form a second contact hole having a diameter larger than a distance between the wires. Here, the conductive layer pattern is not exposed by the wet etching process and is subsequently surrounded by the silicon nitride layer pattern, the capping layer pattern, and the spacers. A contact plug is placed to fill the second contact hole, and the contact plug is a conductive layer. Therefore, the semiconductor device having the second contact hole can reduce a contact resistance between the contact plug and the semiconductor substrate compared with a case having the first contact hole.
However, when the size of a pitch between the two wires is reduced due to reduction of a design rule of the semiconductor device, it is difficult to lower a contact resistance between the contact plug and the semiconductor substrate by using the second contact hole. Also, since the first contact hole is formed by using the spacers placed on the side walls of the wires, it is more difficult to form second contact hole having the diameter larger than the distance between the wires.
Embodiments of the invention address these and other disadvantages of the conventional art.